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Integrated Circuit Systems, Inc.
ICS9148-75
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Mother Boards
General Description
The ICS9148-75 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumProTM, AMDTM or CyrixTM. Sixteen different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-75 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.
Features
* Generates the following system clocks: - 3 CPU(2.5V/3.3V) up to 100MHz. - 6 PCI(3.3V) @ 33.3MHz (including one free running PCICLK) - 3AGP(3.3V) @ 2 x PCI - 13 SDRAMs(3.3V) up to 100MHz - 1 REF (3.3V) @ 14.318MHz - 1 - 48MHz (3.3V) fixed Skew characteristics: - CPU - CPU<250ps - CPU(early) - PCI : 1-4ns - AGP - PCI: 250ps - PCI - PCI <500ps Supports Spread Spectrum modulation & I2C programming for Power Management, Frequency Select Efficient Power management scheme through power down PCI, AGP and CPU_STOP clocks. Uses external 14.318MHz crystal 48 pin 300mil SSOP.
*
* * * *
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:3)
9148-75 Rev C 3/01/00
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9148-75
Preliminary Product Preview Pin Descriptions
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6 7 FS11, 2 8 10, 11, 12, 13 14 15 17 PCICLK0 FS21, 2 PCICLK(1:4) VDD5 BUFFERIN CPU_STOP# SDRAM 11 18 28, 29, 31, 32, 34, 35,37,38 20 PCI_STOP#1 SDRAM 10 SDRAM (0:9) AGP_STOP#1 SDRAM9 21 19,30,36 23 24 25 MODE1, 2 48MHz 26 41, 43, 44 40 42 46, 47 48 FS0
1, 2
P I N NA M E VDD1 REF0 FS3 GND X1 X2 VDD2 PCICLK_F
TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT PWR IN IN OUT IN OUT OUT IN OUT IN OUT PWR IN IN OUT IN OUT IN OUT OUT PWR OUT PWR
DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Supply for fixed PLL, 48MHz, AGP0 Input pin for SDRAM buffers. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Supply for SDRAM (0:11), CPU Core, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Advanced Graphic Port output, powered by VDD4. Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Feedback SDRAM clock output. Supply for CPU (0:3), either 2.5V or 3.3V nominal Advanced Graphic Port output powered by VDD4. Supply for AGP (0:2)
PD#
1
SDRAM8 VDD3 SDATA SCLK AGP0
CPUCLK(0:3) SDRAM12 VDDL AGP (1:2) VDD4
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9148-75
Preliminary Product Preview Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Pin 20 AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP# 1 1 1 0 0 1 1 1 1 1 0 1 CPUCLK Outputs Stopped Low Running Running Running PCICLK (0:5) Running Running Stopped Low Running PCICLK_F, REF, 48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO Running Running Running Running AGP(1:2) Running Running Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
3
ICS9148-75
Preliminary Product Preview
Functionality
VDD1, 2, 3, 4 = 3.3V5%, TA= 0 to 70C Crystal (X1, X2) = 14.31818MHz
FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CPU,SDRAM (MHZ) 105 110 115 120 125 130 135 140 100 95.25 83.3 75 75 68.5 66.8 60
PCI (MHZ) AGP (MHZ) 35 70 36.67 73.34 38.33 76.66 40 80 41.66 83.32 43.33 86.66 45 90 46.67 93.44 33.3 66.6 31.75 63.5 33.3 66.6 30 60 37.5 75 34.25 68.5 33.4 66.8 30 60
REF, IOAPIC (MHZ) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
4
ICS9148-75
Preliminary Product Preview General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
5
ICS9148-75
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7
Bit (2, 6:4)
Bit 3 Bit 1 Bit 0
Description PWD 0 - 0.25% Spread Spectrum Modulation 0 1 - 0.6% Spread Spectrum Modulation Bit (2, 6:4) CPU CLKs PCI CLKs AGP CLKs 1111 105 35 70 1110 110 36.67 73.34 1101 115 38.33 76.66 1100 120 40 80 1011 125 41.66 83.32 1010 130 43.33 86.66 1001 135 45 90 1000 140 46.67 93.44 Note1 0111 100 33.3 66.6 0110 95.25 31.75 63.5 0101 83.3 33.3 66.6 0100 75 30 60 0011 75 37.5 75 0010 68.5 34.25 68.5 0001 66.8 33.4 66.8 0000 60 30 60 0 - Frequency is selected by hardware select, Latched Inputs 0 1 - Frequency is selected by Bit 6:4 (above) 0 - Normal 0 1 - Spread Spectrum Enabled (center spread) 0 - Running 0 1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency; Bits 2, 6:4 are default to 000
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation 6
ICS9148-75
Preliminary Product Preview
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) CPUCLK3 (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 15 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description (Reserved) PCICLK_F (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 25 26 17 18 20 21 PWD 1 1 1 1 1 1 1 Description AGP0 (Active/Inactive) (Reserved) FS0# (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 8 7 47 2 46 2 PWD 1 1 1 1 1 Description (Reserved) FS2# FS1# AGP2 (Act/Inact) (Reserved) FS3# AGP1 (Act/Inact) REF0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 6: Optional Register for Possible Future Requirements
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications.
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ICS9148-75
Preliminary Product Preview
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-75. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-75. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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ICS9148-75
Preliminary Product Preview
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-75. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-75 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
9
ICS9148-75
Preliminary Product Preview AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP (0:1) clocks. for low power operation. AGP_STOP# is synchronized by the ICS9148-75. The AGP2 clock is free-running and is not affected by AGP_STOP#. All other clocks will continue to run while the AGPCLKs are disabled. The AGPCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less than 4 AGPCLKs. This function is available only with MODE pin latched low.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. AGP_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-75. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
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ICS9148-75
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9148-75 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
11
ICS9148-75
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time Skew1
1 1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP Fi CIN CINX Ttrans Ts TSTAB
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; 66.8 MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq.
0.1 2.0 -100 100 14.318
MAX VDD+0.3 0.8 5
160
UNITS V V mA mA mA mA MHz
27
36
5 45 2 2
pF pF ms ms ms ps ns
Clk Stabilization
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads TCPU-PCI1 VT = 1.5 V; CPU Leads
-500 2
200 5
500 6
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1
1
SYMBOL IDD2.5OP
CONDITIONS CL = 0 pF; 66.8 MHz
MIN
TYP 10 200 5
MAX 20 500 6
UNITS mA ps ns
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
-500 2
Guaranteed by design, not 100% tested in production.
12
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2A VOL2A IOH2A IOL2A tr2A1 tf2A1 d t2A1 tsk2A1 tj1s2A1 tjabs2A1
CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.5
33
TYP 2.6 0.35 -29 37 1.75 1.1
MAX 0.4 -23 2 2 55 250 150 250
UNITS V V mA mA ns ns % ps ps ps
45
50 50 65
-250
165
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 1 tf1
1 1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.8 1.6
MAX 0.4 -40 2 2 55 250 150 250 250 650
UNITS V V mA mA ns ns % ps ps ps ps ps
d t1
45
50 130 40 200
tsk1
tj1s1a tj1s1b
tabs1a VT = 1.5 V, synchronous VT = 1.5 V, asynchronous tjabs1b 1 Guaranteed by design, not 100% tested in production.
1
-250 -650
135 500
13
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -28 mA Output High Voltage VOH1 IOL = 23 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 Rise Time1 Tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 Tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 Skew
1
MIN 2.4
41
TYP 3 0.2 -60 50 1.75 1.5
MAX 0.4 -40 2 2 55 500 150 +250 400
UNITS V V mA mA ns ns % ps ps ps ps
Dt1 Tsk1 Tj1s1 Tjabs1 Tjabs1
VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (with synchronous PCI) VT = 1.5 V (with asynchronous PCI)
45
50 200 50
Jitter, One Sigma1 Jitter, Absolute1 Jitter, Absolute1
1
-250 -400
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma1 Jitter, Absolute1
1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1
1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.1 1
MAX 0.4 -40 2 2 55 250 3 5 6
UNITS V V mA mA ns ns % ps % % %
tf1 1 d t1 1 tsk1
1
45
50 130 2
tj1s1 tabs1a tjabs1b
-5 -6
2.5 4.5
Guaranteed by design, not 100% tested in production.
14
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 1 tf5
1 1
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 2.6 0.3 -32 25 2 1.9
MAX 0.4 -22 4 4 55 3 5
UNITS V V mA mA ns ns % % %
d t5
45 -5
50 1 -
tj1s5 1 tjabs5 1
Guaranteed by design, not 100% tested in production.
15
ICS9148-75
Preliminary Product Preview
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01 F ceramic
16
ICS9148-75
Preliminary Product Preview
Ordering Information
ICS9148yF-75-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
17
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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